COURSE GUIDE
수강 정보
강좌 구분
KOCW
제공처
한경국립대학교
교수·강사
김수찬
비용·방식
원문 확인
학습 기간
상시
— 종료일 미정
강좌 소개
1 Represent gates and combinational logic by concurrent VHDL statements 2 Make a table and derive the characteristic (next state) equation for such latches and flip flops State any necessary restrictions on the input signals3 Given the present state and desired next state of F F determine the required F F inputs 4 Analyze a sequential circuit by signal tracing 5 Given a problem statement for the design of a Mealy or Moore sequential circuit find the corresponding state graph and table 6 Specify a suitable set of state assignments for a state table eliminating those assignments which are equivalent with respect to the cost of realizing the circuit7 Design a sequential circuit using gates and flip flops
핵심 정보
강좌 요약
2012년 2학기
교육 대분류
공학계열
교육 중분류
컴퓨터ㆍ통신
상세 데이터
상세 데이터
강좌 소개
1 Represent gates and combinational logic by concurrent VHDL statements 2 Make a table and derive the characteristic (next state) equation for such latches and flip flops State any necessary restrictions on the input signals3 Given the present state and desired next state of F F determine the required F F inputs 4 Analyze a sequential circuit by signal tracing 5 Given a problem statement for the design of a Mealy or Moore sequential circuit find the corresponding state graph and table 6 Specify a suitable set of state assignments for a state table eliminating those assignments which are equivalent with respect to the cost of realizing the circuit7 Design a sequential circuit using gates and flip flops
교수·강사
김수찬
등록일
2012-08-17
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